The serial data communication scheme used here is called asynchronous because the time between transmitted characters is not fixed, and the transmitting and receiving devices are not synchronized to the same clock, although the individual bits of each character are transmitted at a known baud rate. The line is held at the MARK level when idle; for each character, the receiver must recognize when the character starts and synchronize itself to the transmitter to read the individual bits of the character. This is accomplished by sending each character in a "frame" consisting of a START BIT (a SPACE for one bit period), the bits of the character (least significant bit first), and a least one STOP BIT (a MARK for a least one bit period).
Characters are represented by from 5 to 8 information bits, with 8 bits most common. The 8 bits may represent the extended-ASCII codes, or the standard ASCII codes followed by a parity bit to allow the detection of single-bit errors. The STOP bit is essentially an enforced IDLE before the next START bit; it gives the receiver time to complete processing of the received character (e.g., compute and check the parity of the received character) and allows for slight differences between the transmit and receive clocks.
Common baud rates for 8-bit (or 7-bit and parity) characters with 1 start and 1 stop bit are 300, 1200, 2400, 4800, 9600, and 19200 baud, corresponding to 30, 120, etc. characters per second (since the start and stop bits must be included in the bit count); old-fashioned mechanical teletypes ran at 75 baud using characters with 1 start, 5 (Baudot code) data, and 1.5 stop bits, or at 110 baud using characters with 1 start, 8 data, and 2 stop bits, i.e., at 10 characters/sec.
Receivers typically use an internal clock that is 16 times the baud rate. Reception of a character starts when the receiver detects a 1-to-0 (IDLE-to-START) transition. The receiver then waits for 8 block periods (.5 bit period) and tests the line again: if the signal is now 1 this is considered a false start and the receiver goes back to looking for another 1-to-0 transition; if the signal is still 0 it was a valid start and the remaining bits will be sensed every 16 block periods (1 bit period) thereafter. This approach synchronizes the receiver to the transmitter to within 1/16 of a bit period at the beginning of each character, and tends to place the times at which the signal is sampled at the middle of each bit period, thus maximizing the tolerance for differences between the receiver's and transmitter's internal clocks. The receiver will indicate a "framing error" if the signal is not at the 1 level at the middle of the stop bit period. The next START transition may occur immediately thereafter.