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ECE 411 : Computer Organization and Design |
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Home Page
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Spring 2008 Lecture Notes·
Introduction (ppt)
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Instruction Set Architecture (ppt) H&P Chapter 2
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Single Cycle CPU Design (ppt) H&P: 5.1-5.4
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Multi Cycle CPU Design (ppt) H&P 5.5, 5.6
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Virtual Memory (ppt) H&P 7.4
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Caches (ppt) H&P 7.2, 7.3
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More Caches (ppt) H&P 7.2, 7.3
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Caches and Virtual Memory(ppt) H&P 7.2, 7.3
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Pipelining(ppt) H&P 6
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Pipelining Hazards(ppt) H&P 6
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Control Hazards(ppt) H&P 6
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Instruction-Level Parallelism(ppt)
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Dynamic Scheduling(ppt)
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More Dynamic Scheduling(ppt)
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Hardware-level Speculation/ Some software tricks(ppt)
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Hardware Multithreading(ppt)
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Heterogeneous Multi-core Computing(ppt)
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Multiprocessor Issues(ppt)
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More Multiprocessor Issues(ppt,pdf)
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VLIW/Vector Processors(ppt,pdf)
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In a burst of
symbolism, Intel engineers crafted an image of a shepherd looking after a
two-headed ram. The real purpose of the Intel 8207 chip: a dual-port RAM
(random access memory) controller. Credit: Silicon Zoo |
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