Helpful Tips and Tricks
1. How to save yourself from
endless grief when modifying an MP. 1. How to save yourself
from endless grief when modifying an MP. 2. How do I initialize
my variables/signals? 3. Where do I go when I get stuck on something in the lab? 5. Where can I get help for the Logic Analyzer 6. The synthesis tools are locking up with no explanation, or I think they are locking up but I'm not sure. 7. Synthesis is failing, and I don't know why or where to look for error info. 8. Synthesis is giving mysterious errors (Error message: precision stopped by signal 6) running on eelnx and dcllnx machines. 9. I debugged my design in ModelSim, but when I upload the .bit file onto the FPGA, it doesn't work. What do I do? 10. I'm not getting any output on the Logic Analyzer. 11. Certain signals aren't behaving the way I'm expecting them to on the logic analyzer. 12. Modelsim shows correct behavior, but the logic analyzer shows none of my signals, and my design doesn't work.
2. How do I initialize my variables/signals?
3. Where do I go when I get stuck on something in the lab?
4. SSH doesn't work correctly
5. Where can I get help for the Logic Analyzer
6. The synthesis tools are locking up with no explanation, or I think they are locking up but I'm not sure.
7. Synthesis is failing, and I don't know why or where to look for error info.
8. Synthesis is giving mysterious errors (Error message: precision stopped by signal 6) running on eelnx and dcllnx machines.
9. I debugged my design in ModelSim, but when I upload the .bit file onto the FPGA, it doesn't work. What do I do?
10. I'm not getting any output on the Logic Analyzer.
11. Certain signals aren't behaving the way I'm expecting them to on the logic analyzer.
12. Modelsim shows correct behavior, but the logic analyzer shows none of my signals, and my design doesn't work.
After every little "breakthrough" in your code, copy your file(s)
and change the name to reflect a new version number. This way you can always
go back to something that worked 2 hours ago.
I always recommend using a "reset" signal. When your reset is set
to activated, set all your values to their default. Make sure that this if
statement takes priority and the reset signal is on the sensitivity list.
1) Try debugging your problem in Modelsim
2) Debug using the Logic Analyzer
3) Check out the documentation section on the website
4) Look through this FAQ
5) Post to the webboard, or look for similar posts on the same topic.
6) Go to Brian or Kris' office hour
7) Cry and ask your mom why she let you choose ECE as your college
major (use this only as a last resort)
WinSCP, PuTTY, and PSFTP are all various free programs you can
use as replacements to SSH.
There is no hard manual, your best bet for help with the software is
the in-program help menu. If that doesn't get the job done, ask the
TAs at office hours. Often students wonder why it is taking a long time
to sample and capture data. This is often because the sampling memory is
set too large. Keep in mind you can decrease this parameter.
If you are sure the tools have locked, the only way to stop them is
to kill -9 (*nix command) the processes.
It sometimes isn't obvious when the tool has locked up. You tend to get a
feel for it after watching it run a few times. However, that isn't always
very helpful. A better way is to look at the generated logs.
../ece412_lib/ps/mp1_cp1_struct/mp1_cp1_struct
In that directory (example for mp1 only), usually created during synthesis
you will find a number of .rep files and a precision.log file. You can examine
both with any text reader.
../ece412_lib/ps/mp1_cp1_struct
On this level is another precision.log that will give you basically the same info.
There may also be some directory called
../ece412_lib/ps/mp1_cp1_struct/mp1_cp1_struct_temp/
which will also have a log file.
Check these log files because they usually have more information then you can get
from a locked Precision Synthesis GUI
When Precision Synthesis gives an assertion fail and closes on its own while
synthesizing your design, all the log information you see in the precision
synthesis screen before it closes will be in the log file, which is located
inside the "ps" directory. And an additional error message will be at the
bottom as well. There is also some errors in a precision.log file in the
_struct_temp directory.
Try running synthesis on a Sun EWS machine (glsn or dclsn).
Use the logic analyzer to debug the physical signals in your design. It is very
common to make some assumption in ModelSim that turns out to be very different in
reality, for example signal timings for the I2C bus. Debugging is a step by step
process, with ModelSim being step one.
The most common reason for this is you didn't replace the .ucf file generated by
Precision Synthesis with the .ucf file available for download in the MP section of
the ECE 412 website. The ucf Precision generates is blank, and in order for the
debug outputs to be set up correctly, you must use the one from the website.
There is a good chance those signals are INOUT signals in the design, meaning they
can serve either as an input or an output signal, depending on the current state.
Since INOUTs get driven by 2 or more sources, we need to avoid the possibility of a
short (one source driving a 1 and another driving a 0). Thus whenever your design is
not actively driving a 1 or 0, you must output high impedance, which is 'z'. Be very
careful while debugging to check for instances when two sources are trying to drive the
same INOUT signal at the same time.
Double check to make sure you have downloaded the .ucf file supplied on the MP website
and replaced the blank one in the same directory as your .edf file before synthesis.
This is a necessary step to get a working design or use the logic analyzer.
Generic VHDL Questions
1. Can more than one process
update a signal?
2. What is the difference between a signal
and a variable?
1. Can more than one process update a signal?
No. This tends to cause race conditions. (Which process should have updated the signal?)
2. What is the difference between a signal and a variable?
A signal is a global object that can be read by multiple processes and updated in one process. It is updated when the process finishes executing one iteration. A variable is a process-specific* object that is updated DURING the process execution. It should be used for temporary objects. Variables are supposed to keep their last state when the process runs a following iteration. I have heard that variables are not treated well by the compiler as opposed to signals. If a problem arises with using a variable, I suggest trying to replace your code segment so you can use signals. * A variable can be shared among processes using shared variables. This is highly discouraged since you do not know what the final state of the variable will be after all processes have executed.
Helpful Tips and Tricks
1. Is there some easy way to force 11 clock pulses in the .do file other than to specify each clock pulse? 2. In the .do file, how do you specify a value for a signal that is more than one bit? 1. Is there some easy way to force 11 clock pulses in the .do file other than to specify each clock pulse? 2. In the .do file, how do you specify a value for a signal that is more than one bit?
Suppose you want to run the clk for only 16 pulses, you could use this command
force /CLK_32MHz 0 0, 1 16 -repeat 32 -cancel 512
The 512 comes from 16 cycles x 32ns a cycle.
Suppose you have a bit_vector(0 to 3) - you can specify its value in the following ways.
character literal - 1111
binary - 2#1111
decimal - 10#15
hex - 16#F
MP1 Specific Questions
1. Where do I find documentation on
the PS/2 protocol?
2. Can you please summarize the important information
for me?
3. What do we do with the files we're given for MP1CP2 and other checkpoints, use them or start from a blank slate?
4. What is an example of a good project to choose for MP1 CP3?
1. Where do I find documentation on the PS/2 protocol?
From the MP1 handout.
2. Can you please summarize the important information for me?
From the MP1 handout: 1) Start bit is always '0' 2) Read data on falling edge 3) Stop bit is high 4) You may pause future transmission of data by holding the clock low. 5) If using inout for clk, drive it to 'Z' when you are not driving it.
1) Start bit is always '0' 2) Write data on rising edge 3) Stop bit is high 4) You may pause future transmission of data by holding the clock low. 5) If using inout for clk, drive it to 'Z' when you are not driving it. 6) You have to actively drive the data line and clk, except for ACK.
There are also break codes which use more than one byte of information. For more information, refer to the MP1 documentation
3. What do we do with the files we're given for MP1CP2 and other checkpoints, use them or start from a blank slate?.
4. What is an example of a good project to choose for MP1 CP3?.
The given files for CP2 is a blank design file with some additional
I/O pins, such as PS2_CLK and PS2_DATA. It is intended you will use these
files as a starting point and build your design on top of this.
This checkpoint is mostly to give you some more experience working with
the equipment in the lab. Some rules of thumb when thinking about what to do:
1) Checkpoint 3 should be approximately as much additional complexity as
checkpoint 2 was. (By additional complexity, we mean that you shouldn't count
any parts of checkpoints 1 and 2 that you re-use.)
2) As far as creativity is concerned, what we're looking for here is a design that
does something "interesting", meaning that it should do something you can describe
reasonably well. A list of "well, when you push this button, this light turns on,
and when you push the other one this other light turns on" isn't a good description.
"Plays a version of Pong on the LEDs by bouncing a lit LED back and forth and requiring
the player to push a button at the right time" is a good description.
We'll also post example projects from past semesters for CP3.
MP2 Specific Questions
1. How do I run the TA reader program on the ipaq?
2. The TA_reader program outputs "Bad file descriptor" when we connect it to our design.
3. For CP2, do we have to implement attribute write? This option is in the ta_reader program, but it doesn't do anything.
4. Why can't I see any kernel messages in the /var/log/ directory on the ipaq?
5. How do I simulate the blockRAMs in ModelSim?
6. Blockrams work in simulation but not reality.
1. How do I run the TA reader program on the ipaq?
Navigate to the directory where ta_reader is located and type "./ta_reader".
2. The TA_reader program outputs "Bad file descriptor" when we connect it to our design.
This is not a problem with the ta_reader program itself, it means you are incorrectly implementing the PCMCIA transaction. First load the ta_solution.bit file to make sure the connections are working. Then try your CP1 design and make sure cardctl ident 0 returns the correct data. Another thing to check is that you have IREQ_RDY_H tied to high when you are returning any data.
3. For CP2, do we have to implement attribute write? This option is in the ta_reader program, but it doesn't do anything.
No, you don't need to implement this. If you'd like you can put it in your software to mimic the ta_reader, but we won't be checking for it.
4. Why can't I see any kernel messages in the /var/log/ directory on the ipaq?
You need to be sure syslogd and klogd are running. Run "/etc/init.d/syslog start" to start it up.
5. How do I simulate the blockRAMs in ModelSim?
Using BRAM with ModelSim Example BRAM code
6. Blockrams work in simulation but not reality.
If you grabbed the BlockRAM VHDL Initialization code from the Xilinx documentation, there are comments in there that say: "--synopsys " and something else, where something else includes translate_off, translate_on, dc_script_begin, and dc_script_end Delete these comments, and anything else like them. They are similar to a pre-processor directive for the synthesis tools, and cause strange, unexpected things to happen during synthesis. The TAs recommend you use the blockram code supplied in the example BRAM. This code should be sufficient for using the on-board BRAM.
MP3 Specific Questions
1. Which cycles does the VGA device display pixels, and what timing does it require?
1. Which cycles does the VGA device display pixels, and what timing does it require?
VGA Timing Information
Reports
Make sure to explicitly create a design, implementation, testing, and results section for EACH CP, even if you don't have much to say in one section. In each design & implementation section, include a subheading for EVERY component that you designed. For each component in the design section, explicitly state the interface of the component (inputs and outputs), and its overall purpose/function. For each component in the implementation section, explain your implementation, walk through the code/state machine/block diagram, whether you considered alternative methods of implemtation. In testing, explain what tests you performed, and the problems you debugged. Try to save your modelsim waves and logic analyzer screenshots as you debug your CPs, and include them in testing or results. Include a conclusion. Summarize here the problems you had, how you fixed them, your overall reflections on what you learned and the lab in general. In the appendix, include all block diagrams, VHDL, or state machines that YOU created, not given code. Overall, make sure to use any and every section to reflect on what you could have done better looking back, whether it be design, implementation of a component, testing strategy, whatever. The purpose of these reports (and the lab) is to get you to reflect on your engineering habits, and improve upon them, so try to use this space to do that.
Last updated 1/11/2007 12:31:33 PM