Machine Problem 1

MP1 Handout

HDLDesigner Given Files
Required Files for this checkpoint.
Designed in HDLDesigner and to be unpacked in your ece412 work directory.
Follow the specifications as listed in the MP handout.

UCF File
This file needs to be in the same directory as your .edf file when you run ngdbuild

HDLDesigner Given Files
Required Files for this checkpoint.
Designed in HDLDesigner and to be unpacked from the same directory as the mp1_cp1 given files

UCF File
This file needs to be in the same directory as your .edf file when you run ngdbuild

TA Solution Bit File
You may load this bit file on the XUP board to see the expected output.
Note that the word "dead" is displayed on the 7-segment when you hold down the UP and DOWN buttons on the XUP board.
Do not implement such funtionality in your design as it is used to distinguish between the TA solution bit file and a student's bitfile.

Use the resources on the XUP board to create your own design. You may build on top of your CP2 design.
We provide you with a skeleton design if you wish to create CP3 in a new module. If you build on top of your CP2 design, make sure to print your schematics before editing the project.
HDLDesigner Given Files
Optional Files for this checkpoint.
Designed in HDLDesigner and to be unpacked from the same directory as the mp1_cp1 given files

UCF File
This file needs to be in the same directory as your .edf file when you run ngdbuild
Rename this file to mp1_cp3.ucf before generating the bit file.

Some CP3 Examples

Take a SanDisk 1.0GB CompactFlash disk from the lab and put it into the CompactFlash slot on your XUP board.
Open HyperTerm and configure per mp doc instructions. At the login prompt...
username: root
password: root
Explore the linux environment.

Machine Problem 2

MP2 Handout

• Basic Instructions
  • Follow EDK Tutorial
  • Import Custom Core
  • Write ASCII-to-Hex Converter in vhdl. Attach to custom core.
  • Run executable inside Linux to see the hardware-software interaction
  Checkpoint 2 Document
  • Basic Instructions
    • Create your own CUSTOM pcore
    • Write a VHDL median filter. Accepts at least 7 inputs and computes the median value
    • Demo design to TA
  
  
  Checkpoint 3 Document
  • Basic Instructions
    • Create your own Linux device driver to interface with your CUSTOM pcore
    • Write a Linux program that initiates a median filter transaction.
    • Demo design to TA
      
      
    Incomplete Driver
    John Kelm Paper on Linux
  
  
  

  Machine Problem 3

  MP3 Handout

  Checkpoint 1
  • Basic Instructions
    • 1. Implement in VHDL a component capable of generation of correct VGA synchronization timing.
    • 2. Import your component into the EDK to be able to read from DDR memory.
    • 3. Display the image stored in memory on screen.
    • 4. Watch the web board for support code and helpful hints.
    
    ISE Starter Project
    
    ISE Starter Project with write_sel signal in buffer
    
    Tip 1. Use hierarchy, it is your friend.
    Tip 2. Remember that you will need to read from DDR and write it to your local line buffer.
    Tip 3. Only need to support 640x480@60hz resolution. (Frame buffer is built to support up to 1024x768@72)
    Tip 4. Use ModelSim, ModelSim, ... oh and ModelSim.
    Sample pic to display
    Raw RGB files and DDR loader
    VGA timing specs and illustrative picture
  Checkpoint 2
  • Basic Instructions
    • 1. Implement a YCrCb to RGB converter and add it to your CP1 design
    • 2. Alter your CP1 design to handle the different word packing in the DDR for YCrCb
    
    Demo code
  Checkpoint 3
  • Basic Instructions
    • 1. Build a DDR burst write block to move data from local buffer into the DDR
    • 2. Parse the YCrCb stream for actual data to write to DDR
    • 3. Program the ADV7183b chip using the I2C protocal
    • 4. Integrate this design into your overall project to have a real time 640x480@60 video displaying on the LCD monitor from the camera
    
    An I2C programming netlist has been provided for you for early debugging. You are responsible for writing your own vhdl to replace this file in the final design
    You may have to handle plb master arbitration with the bus lock signal to make sure your data is written and read without problems from ddr
    Read online documentation to see where real data is in the YCrCb stream.
    TA Solution Bit File
    You may load this bit file on the XUP board to see the expected output.
    
  
  

  Final Project

  Past projects and ideas

  Additional files
  The zip files contain the pin mappings for both expansion ports. Instructions on which ports to add to your design are included in the UCF files.

• SRAM UCF files
• USB UCF files
• Bit file for use with MemUtil
• The Xilinx ISE project used to create that bit file