ECE 412 MP Report Guidelines

Reports should contain the following sections:

1. Introduction

   Provide a brief overview of the functionality of each of your checkpoints.  As functionality is 40% of lab grading, delineate all working features of your design.  For example:
   

     "In CP3, I implemented a programmable clock using the 7 segment displays.  A separate push button is used to display hours/minutes/seconds, and is programmable by entering the new time via a ps2 keyboard.  The row LEDs flash on each second."

     In addition, please number all of your pages and include a table of contents at the beginning of your report.  A separate table of contents should be used for the appendix.

2. Each of the following 3 subsections should be grouped by checkpoint:
   
   1. Design

      Give a component by component description of your design.  Without describing VHDL implementation, discuss the interface each block provides, and the specific function of that block. This section should also include the reasons why you decided to partition the system as such.  Also, discuss any design alternatives that you considered.

      Explaining how you wired the system up by describing each signal is not necessary.

   2. Implementation

      Describe the necessary details for implementing each component in VHDL.  If using a state machine, you should explain what each state or group of states do, as well as the transitions along the critical path.  If using custom VHDL, explain what processes are necessary, and their corresponding implementation. Describing individual signal names and how they are assigned is too low-level for what we need to understand your implementation.

      This section should also include a discussion of implementation alternatives.  What would you do to make your implementation more efficient, easier to understand, with fewer states, etc.  On the other hand, we also want you to emphasize anything that is particularly clever about your implementation.

   3. Testing

      Describe your testing strategy for the checkpoint, in particular what you did to generate input sequences for individual modules to test them before integrating them into a complete design. Please do not list individual tests that you ran, but do give enough detail to convince us that you performed enough testing to be reasonably sure that your design works. For example, if the checkpoint asked you to implement a 32-bit adder, you might describe your strategy for verifying that all of the bits of the adder and the carry chain worked correctly without exhaustively testing all of the possible inputs to the adder.

   4. Results

      Any figures specifically requested in the MP that do not fit in the above sections, such as simulation/logic analyzer traces and screenshots, should be placed in this subsection.  You must caption all figures with a short description.

      Place any VHDL related schematics (state diagrams, block diagrams, etc.) and code in the appendix.

3. Conclusion/Lessons Learned
   • Briefly sum up what does/does not work in your designs.
   • Were there any significant problems that appeared, and if so, what did you do to resolve them?
   • Complaints about lack of time, shortage of boards, etc. do not belong in your report.  Please inform the course staff before the MP due date so we can fix any problems as early as possible.

4. Appendix
   • Include all custom VHDL code you write.  If you reuse code in more than one checkpoint, please place that code only with the first checkpoint in which it is used. Please print code two columns/page (using mpage) and double sided if possible to save space.
   • Any C code that you write should also be included in the appendix.
   • If you use an hdldesigner state machine, please include a screenshot of the FSM diagram, and not any of the auto-generated code. 
   • Include the any hdldesigner block diagrams (sometimes called the "schematic") for each checkpoint. 
   • The aforementioned materials should be ordered by checkpoint, and be prefaced by a table of contents. 

Other notes:

• Repeated spelling and grammar errors will be penalized.
• No length requirement - use only enough pages to satisfy the requirements in a concise manner.

Last updated 1/26/2005 3:46:05 PM