ECE 543 - Digital System Testing and Design for Testability

Machine Problem


HITEC/PROOFS Manual

Machine Problem
Logic Simulation Algorithm

Circuits and test vectors for debugging purpose.
c17.lev
c17.vec
c17.out
c432.lev
c432.vec
c432.out
c1908.lev
c1908.vec
c1908.out
c2670.lev
c2670.vec
c2670.out
s27.lev (Sequential Circuit)
s27.vec
s27.out
s298.lev (Sequential Circuit)
s298.vec
s298.out
s349.lev (Sequential Circuit)
s349.vec
s349.out

Here are MINTEST vectors and HITEC vectors. More test vectors can be checked out at IGATE website.

Combinational ISCAS85 circuits and sequential ISCAS89 circuits are here. *.lev files are levelized netlist and *.eqf files are fault list after equivalence collapsing.

ATOM code is provided here.  It is able to perform test generation and fault simulation for ISCAS combinational circuits. It can be used for debug purpose.

Send any questions to liyang@crhc.uiuc.edu
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