ECE 598 BL

Design & Synthesis of SoC

Fall 2007

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DATE	LECTURE SLIDES	ACCOMPANYING MATERIAL
08/23/07	Lecture1
08/28/07	Lecture2	Tutorial: System on Chip Design
08/30/07	Lecture3	IBM CoreConnect Bus Cores
09/04/07	Lecture4
09/06/07	Lecture5	Improving Embedded Software Design and Integration in SOCs
09/11/07	Lecture6
09/13/07	Lecture7	HW/SW Co-Design for Platform FPGAs
09/18/07	Lecture8
09/20/07	Lecture9	Performance Analysis of Embedded SW Using Implicit Path Enumeration
09/25/07	Lecture10	Force Directed Scheduling for the Behavioral Synthesis of ASIC’s
09/27/07	Lab Review
10/02/07	Lecture11	Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications
10/04/07	Lecture12
10/09/07	Lecture13	- Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication - Research Project Overview
10/11/07	Lecture14	Application Specific Instruction Generation for Configurable Processor Architecures
10/16/07	Midterm	Midterm
10/18/07	Lecture15	The Extended Partitioning Problem: HW/SW mapping & Implementation-Bin Selection
10/23/07	Lecture16	A Timing Driven Module-Based Chip Design Flow
10/25/07	Lecture17	A HW-SW Codesign Methodology for DSP Applications
11/06/07	Lecture18
11/08/07	Lecture19	Interface Cosynthesis techniques for embedded systems
11/13/07	Lecture20	DESERT-Technical Report Interactive Learning 1
11/15/07	Lecture 21	Interactive Learning 2
11/20/07	Break	Break
11/22/07	Break	Break
11/27/07	Lecture 22	Interactive Learning 3
11/29/07	Lecture 23	Interactive Learning 4
12/04/07	Lecture 24	Interactive Learning 5
12/06/07	Lecture 25	Interactive Learning 6